RTL Synthesis (Synopsys Design Compiler, Cadence Genus, or equivalent)

Synopsys Design Constraints (SDC) development and optimization

Timing analysis and closure (Static Timing Analysis - STA)

Logic Equivalence Checking (LEC) and Formal Verification (FV)

Physical Design concepts (floorplanning, placement, routing)

EDA tool expertise (Synopsys, Cadence, Mentor Graphics tools)

Verilog/VHDL HDL understanding

Scripting languages (Tcl, Python, Perl, Shell scripting)

Design methodology and flow understanding

Library characterization and optimization

Power analysis and optimization techniques

Constraint management and ECO (Engineering Change Order) implementation

Strong analytical and problem-solving abilities

Excellent communication and interpersonal skills

Ability to work effectively in cross-functional teams

Attention to detail and commitment to quality

Time management and ability to handle multiple projects simultaneously

Proactive approach to learning and staying updated with industry trends

Documentation and technical writing skills

Collaborative mindset with willingness to mentor junior team members