Static Timing Analysis (STA) tools: PrimeTime, Tempus, or similar

Synopsys Design Constraints (SDC) and timing constraint definition

Digital design and VLSI fundamentals

RTL design languages: Verilog, SystemVerilog, or VHDL

Physical design concepts: placement, routing, and clock tree synthesis

EDA tool flows and design automation

Timing models and characterization

Cross-corner and multi-mode analysis

Design verification and validation methodologies

Scripting languages: Perl, Python, or Tcl for automation

Version control systems: Git or SVN

Strong analytical and problem-solving abilities

Excellent communication and presentation skills

Ability to work effectively in cross-functional teams

Attention to detail and commitment to quality

Self-motivated with strong work ethic

Ability to manage multiple projects and priorities

Proactive approach to learning and professional development

Collaborative mindset with willingness to mentor junior engineers

Time management and organizational skills

Adaptability to evolving technologies and methodologies