SystemVerilog/Verilog HDL

UVM (Universal Verification Methodology)

Cadence tools (VCS, Xcelium, Incisive)

Synopsys tools (VCS, Verdi)

Mentor Graphics tools

Functional coverage and code coverage analysis

Simulation and debugging

Assertion-based verification (SVA)

Testbench development

Waveform analysis and debugging

Version control systems (Git, SVN)

Scripting languages (Perl, Python, Shell)

FPGA verification (optional)

Formal verification tools (optional)

Strong analytical and problem-solving abilities

Excellent communication and presentation skills

Team collaboration and interpersonal skills

Attention to detail and quality focus

Time management and ability to meet deadlines

Adaptability and willingness to learn new tools and methodologies

Documentation and technical writing skills

Mentoring and knowledge-sharing capabilities

Initiative and proactive approach to problem-solving

Cross-functional collaboration with design and integration teams